A. Technical Field
The present invention relates generally to memory devices and more particularly, to a modular design and layout of a multiport memory bitcell having an expandable number of access ports.
B. Background of the Invention
Memory is an essential part of any computation system. A typical memory system may be viewed as a collection of sequential locations, each with a unique address and capable of storing information. Memories are broadly classified based on their functionality as Read Only Memory (“ROM”) or Random Access Memory (“RAM”). Random access memories are further differentiated in static (“SRAM”) or dynamic (“DRAM”) RAM, depending on how the data is stored in the memory bitcell. Memory bitcells can have one or more ports to access stored data. Memory bitcells with multiple ports are typically referred to as multiport memory bitcells. A memory that uses such multiport memory bitcells enables multiple system elements to directly and independently access the contents of such multiport memory.
As shown in FIG. 1, a typically six transistor (“6T”) SRAM bitcell comprises crossed-coupled inverters 102a, 102b and two pass devices 104a, 104b creating a differential port used to read from or write to the bitcell. In this example, both read or write operations are implemented differentially via two bit lines, BL 107a and BLN 107b. The gates of two pass transistors in the bitcell are connected to a common wordline WL 107c. The cell is provided voltage via lines Vss 111a and Vdd 111b. 
The number of ports within the bitcell may be increased by designing additional pass devices to the basic storage node. These additional ports may be dedicated to performing write operations while others are dedicated to performing read operations. A differential port may be used for either read or write operations, and employs two bitlines carrying complementary data for the write operation. A single-ended port may be used only for read operations and employs a single bitline. The differential port provides relatively fast access speeds due to the limited bitline swing required to produce a detectable differential signal that can be sensed by a sense-amplifier. Comparatively, a single-ended read port is relatively slower and requires a bitline to develop much larger swings in order to drive the next stage of logic circuitry. Single-ended read ports typically employ significantly larger devices than the pass devices in write ports.
FIG. 2 shows an exemplary dual port bitcell having a differential port A, bitlines 208a, 208b and a single ended port B for bitline 209. A wordline 208c is provided for port A while a separate wordline 209c is provided for port B. When additional ports are attached to the cross-coupled inverter of a multiport cell, sufficient read, write and static noise margins need to be ensured. When designing a bitcell, these margin parameters need to be weighed against the read and write speed requirements of the cell. For example, pull-down devices on differential ports need to be properly designed to provide sufficient read and noise margin while not overly reducing the write speed of the ports. This tuning of the pull-down devices is less sensitive in single-ended ports and does not affect the beta ratio, read margin, and static noise margin of the cell. Accordingly, designers prefer to use single-ended ports for read ports and differential ports for write ports, which results in multiport cells having a combination of single-ended and differential ports. Furthermore, because of the different tuning requirements needed for various combinations of multiport cell requirements (e.g., the number of write vs. read ports), each multiport bitcell is typically designed from “scratch.”
The design process for multiport bitcells is often complex because of performance and density requirements as well as manufacturability rules imposed by various semiconductor fabrication providers. As fabrication processes advance, the yield and performance of memory elements have become increasingly sensitive to process-layout interactions. Design for Manufacturability (“DFM”) rules have been imposed on design layouts and geometries to improve yield on fabricated memory elements and achieve desired electrical results. These rules include requiring that poly gates run in the same direction, that diffusions are not completely enclosed, and a minimization of length of diffusion (“LOD”) effects which reduces the current drive in an NMOS device due to the proximity of the isolation of the channel.
These DFM rules are intended to protect against fatal errors such as short circuits due to excessive misalignments or open circuits caused by excessive narrowing of metal or poly-silicon. These rules often impose significant restrictions on multiport bitcell designs and significantly complicate the design process. The design process is further complicated because it is often difficult to leverage previous multiport bitcell designs into a new design. For example, if a designer wanted to expand the number of ports in a bitcell, he/she may be unable to leverage a significant portion of the smaller multiport bitcell in the new design.
As semiconductor fabrication techniques further advance, it is likely that DFM rules may become even more stringent and further complicate the design process. As a result, the ability to leverage previous bitcell designs when expanding the number ports may become even more difficult.